Tapping into parallelism with transactional memory
Arrvindh Shriraman, Sandhya Dwarkadas, Michael Lee Scott · ;login:: the magazine of USENIX & SAGE · 2009
Multicore system promise to deliver increasing performance only if programmers make thread-level paralelism visible in software. Unfortunately, multithreader programs are difficult to writte, largely because of the complexity of synchronization. Transactional memory (TM) aims to hide this complexity by raising the level of abstraction. Several software, hardware and hybrid implementations of TM have been proposed and evaluated, and hardware support. We describe the principal hardware alternatives, discuss performance and implementation tradeoffs, and argue that a classic policy-in-software, mechanism-in-hradware strategy can combine excellent performance with the flexibility to accomodate different system goals and workload charasteristic.