Design of Single Precision Floating Point Multiplication Algorithm with Vector Support
T.Govindarao, Davinder Kumar · Zenodo (CERN European Organization for Nuclear Research) · 2015
This paper presents floating point multiplier capable of supporting wide range of application domains like scientific computing and multimedia applications. The floating point units consume less power and small part of total area. Graphic Processor Units (GPUS) are specially tuned for performing a set of operations on large sets of data. This paper work presents the design of a single precision floating point multiplication algorithm with vector support. The single precision floating point multiplier is having a path delay of 72ns and also having the operating frequency of 13.58MHz.Finally this implementation is done in Verilog HDL using Xilinx ISE-14.2.