Implementation-Independent Functional Test Generation for RISC Microprocessors
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik · 2019
We propose a generic strategy for formalized synthesis of Software-Based Self-Test (SBST) for testing microprocessors with RISC architecture with the goal to achieve high gate-level fault coverage without knowing the gate-level implementation detail, and to have well-structured compact test, which can be easily unrolled on-line during test execution. The high-level model of the microprocessor is derived from the instruction set and from the architectural features introduced for increasing performance, like pipelining, forwarding, hazard handling, prediction, etc. A novel high-level functional control fault model is introduced, which has the capability of covering a broad class of gate-level faults. For the functional testing of data-path, bitwise pseudo-exhaustive test method is used. A novel method for measuring the high-level fault coverage is proposed. As an added value of the method, an efficient approach for identifying low-level redundant faults is described. Experimental results demonstrate high fault coverage achieved for MiniMIPS processor without using any information about gate-level implementation details.