A 2 $\times$ 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems
Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka · IEEE Journal of Solid-State Circuits · 2019
The world's first 2 x 30k-spin multi-chip CMOS annealing processor (AP)-based on the processing-in-memory approach for solving large-scale combinatorial optimization problem-was developed. To expand the bit width of coefficients and enhance the scalability of the AP, it has three key features: an expandable and high-accuracy spin operator for local communication, a highly integrated spin circuit using direct access to SRAM, and a low-latency inter-chip interface that does not affect the runtime or results of the annealing process. The AP is fabricated on the basis of 40-nm CMOS technology. It was experimentally demonstrated that the spin-flip ratio of the processor agrees well with theoretical values based on the Gibbs distribution over a wide temperature range. As a result, under two-chip operation with 2 x 30k spins, the AP achieves an annealing time of 22 μs, which is 455 times and 2.6 x 104times faster than those achieved by our previous CMOS-AP and a conventional CPU, respectively. Moreover, its energy efficiency is 1.75 x 105 times higher than that of a conventional CPU-based algorithm.