A Half-Rate Built-In Self-Test for High-Speed Serial Interface using a PRBS Generator and Checker
Ram Ratnaker Reddy Bodha, Sahar Sarafi, Ajinkya Kale, Michael Koberle, Johannes Sturm · 2019
In this work, a half-rate built-in self-test (BIST) system is proposed to enable bit error rate measurement without the need for off-chip subsystems such as memory and PRBS generator. The proposed BIST system consists of a half-rate series-parallel PRBS generator with a unique pattern to self-synchronize the received data stream with the reference data at the half-rate bit error checker. The proposed BIST system schematic is implemented in 0.9V, 28nm CMOS technology for a 10 Gbps on-chip serial data transmission system. The RMS jitter at the PRBS generator output is evaluated to be 1.45 ps with post-layout simulation considering the output loading in nominal conditions. The PRBS generator and bit error checker consumed total power of 5.225 mW in nominal conditions.