High Speed Full Custom Parallel Multiplier Based on Radix-4 Booth
Yashael Faith Arthanto, Sayyid Irsyadul Ibad, Trio Adiono · 2019
Multiplier is one of the most critical block which is extensively used in many digital systems. However, multiplier consumes large chip area and needs long processing time. Therefore, to improve system computational performance, high speed multiplier design is required. Radix-4 booth multiplier has faster processing time than conventional multiplier. This paper proposed a high speed multiplier based on Radix - 4 booth multiplier. The radix-4 booth multiplier is designed with fully combinational parallel architecture to achieve multiplication processing within one clock cycle. The proposed design is a full custom design using 130 nm CMOS technology. The DRC and LVS are used to verify the design. The proposed design layout has dimension of 207.5 μm × 200.005 μm and an area of 41,501.0375 μm2. The worst case delay of this design is 378.74 ns and can be operated at 2.5MHz clock frequency.