Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL
Austin Rovinski, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve X. Dai, Ritchie Zhao, Dustin A. Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Chun Lan Zhao, Michael Bedford Taylor, Ronald Dreslinski, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath · IEEE Solid-State Circuits Letters · 2019
This letter presents a 16-nm 496-core RISC-V network-onchip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a peak energy efficiency of 314.89 GRVIS/W, and a record 825320 CoreMark benchmark score. Unlike previously reported [1], this new score was obtained without modifying the core benchmark code. The main feature is the NoC architecture, which uses only 1881 μm2per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.