Design and Implementation of 8-bit LFSR, Bit-Swapping LFSR and Weighted Random Test Pattern Generator: A Performance Improvement
Abhilash Bagalkoti, Suhas B. Shirol, S. Ramakrishna, Priyatam Kumar, B S Rajashekar · 2019
The power dissipation during the testing cycle is more than that of the normal working of the chip. One reason is that as the chip size is being diminished the power dissemination of the circuit is likewise lessened. Adding a little overhead to the circuit for the purpose of testing which can remove the use of complex external testing component is the method called as Built In Self Test (BIST). In BIST the LFSR is utilized to produce the irregular patterns for testing of a VLSI circuit. This paper describes of a conventional linear feedback shift register, BS-LFSR and multiple WRTPG.