SoC Security Verification using Property Checking
Nusrat Farzana, Fahim Rahman, Mark Tehranipoor, Farimah Farahmandi · 2019
Security of a system-on-chip (SoC) can be weakened by exploiting the inherent and potential vulnerabilities of the intellectual property (IP) cores used to implement the design as well as the interaction among the IPs. These vulnerabilities not only increase the security verification effort but also can increase design complexity and time-to-market. If the design and verification engineers are equipped with a comprehensive set of security properties at the early stage of a design process, SoC security validation effort can be greatly reduced. In this paper, we propose a property-driven approach to design a secure SoC. Our goal is to develop a comprehensive set of reusable and architecture-agnostic properties acting as security-aware design rules and guidelines. Moreover, we develop metrics from these properties to facilitate quantitative security assessment. Finally, we present design examples to demonstrate the efficacy of our approach under different threat models.