Improving Parallel Testing Efficiency of Memory Chips using NOC Interconnect
Chaneui Hong, Jin-Ho Ahn · The Transactions of The Korean Institute of Electrical Engineers · 2019
Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.