Do Not Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication
Maria I. Mera Collantes, Siddharth Garg · IEEE Embedded Systems Letters · 2019
In this letter, we propose VeritAcc, a novel application that enables secure integration of an untrusted third-party matrix multiplication (MM) hardware accelerator in a system-on-chip containing a trusted general purpose processor. Our solution builds upon the theory of interactive proof (IP) protocols to enable run time verification of each computation executed on the untrusted accelerator and formally guarantees that any incorrect results are detected with high probability. Our novel optimizations in hardware implementation reduces area and performance overhead of VeritAcc. We show that an field programmable gate array (FPGA) prototype of VeritAcc introduces less than 6.25% digital signal processing (DSP) area overhead compared to a baseline untrusted MM accelerator while enabling 11×-69× speed-ups compared with software execution.