Novel Method to Compute Cube Confirming Low Device Utilization on FPGA
Avinash Patil, Srinivas Patil · Helix · 2019
The contribution made by authors in a calculation of a cube of a number includes the digital architectures leading to a computation of cube of an 8-bit binary number which produces the result with reduced hardware utilization on FPGA.The cube is a prominent operation required in many mathematical operations, signal and digital image processing applications.The cube also required in many cryptographic applications as well as trigon arithmetic operations such as taylor series and Mclauren series.The conventional method of finding the cube of a number is faster but required dedicated multiplier block on FPGA and or a large amount of digital gate level resource.The architectural novelty is proposed which can be used at gate level as well as algorithmic level.The cube proposed by authors include features of Vedic mathematics Anurupya sutra, Vertical and crosswise sutra also used, leading to a new better architecture.The cube operation is carried out in VHDL and is compared over conventional as well as Vertical and crosswise based multiplier architectures and provide out better in terms of area and speed optimization.The targeted device used is Spartan XC3S400PQ208 on Xilinx platform.It is observed that the area optimization is achieved with proposed architecture at 2131 gate count compared over 2250 with Vertical and crosswise based cube operation and 8000 gate count with conventional cube calculation method whereas speed enhancement registered over Vertical and crosswise method as proposed method reports 38.348 ns and second one report 43.309 ns.