An 8-bit slice GaAs bus logic LSI for a high-speed parallel processing system
Atushi Kameyama, Katsue Kawakyu, Tadahiro Sasaki, T. Seshita, Tomoki P. Terada, Y. Kitaura, Nagaoki Toyoda, Akira Maeda · 2003
An 8-b slice GaAs bus logic (BL) LSI for a high-speed parallel processing system has been designed with a standard-cell approach, fabricated by a 0.8- mu m WN/sub x/ gate LDD MESFET process, and confirmed to be fully functional. The BL consists of 3376 logic-gates and a 76-b dual-port register file (RF) in a 7-mm*7-mm chip. A 10-ns cycle time has been achieved with a power dissipation of 7 W. By constructing a data transfer network with 48 GaAs BLs, it is possible to realize a data transfer rate of 4 Gb/s (32 b*120 Mcycle/s).>