Adaptation in heterogeneous multi-core SoCs
Amit Kumar Singh, Geoff V. Merrett, Bashir M. Al‐Hashimi · ePrints Soton (University of Southampton) · 2018
Motivation for Heterogeneous Multi-core SoCsThe reliance of embedded computing systems is increasing to heterogeneous multi-core SoCs consisting of different types of cores such as CPU and GPU.An example includes the Samsung Exynos 5422 SoC containing a CPU with four ARM cortex-A15 (big) and four ARM Cortex-A7 (LITTLE) cores, and a GPU with 6 ARM Mali-T628 cores [1].These architectures provide opportunities to exploit distinct features of CPU and GPU cores to meet performance and energy consumption requirements.Further, the cores in these SoCs support dynamic voltage and frequency scaling (DVFS), which can be used to reduce dynamic power consumption (P ∝ V 2 f ).This helps to reduce energy consumption if the extra time taken to run the workload at a lower voltage and frequency can be accounted by sufficient reduction in the power consumption.Open Computing Language (OpenCL) [3] provides an opportunity to write applications that can execute across heterogeneous cores including CPUs and GPUs [6, 8-10].However, since CPU and GPU cores typically handle task/thread and data level parallelism, respectively, the performance and energy consumption of an application varies when executed onto only CPU, only GPU, or both CPU and GPU cores [17].The variation depends upon the kind of parallelism dominating the application.Existing studies have shown significant reduction in execution time and energy consumption when an application simultaneously exploits both the CPU and GPU cores with an appropriate partitioning of threads between them [6]. Related Research and Their ShortcomingsFor concurrently executing applications in a heterogeneous multi-core SoC, e.g., image and MP3 decoding with respective frames per second (fps) requirements, energy-efficient runtime management of applications on SoC resources is desired.Several efforts have been made towards this [4,7,11,13,15].However, they consider cores having the same instruction