28.5 A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4×128 I/Os Using TSV-Based Stacking
Jung‐Sik Kim, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Jin-Guk Kim, Jang-Woo Ryu, Sang-Kyu Kang, SoYoung Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Kye-Hyun Kyung, Joo-Sun Choi, Young-Hyun Jun · 2011
Mobile DRAM is widely employed in portable electronic devices due to its fea-ture of low power consumption. Recently, as the market trend renders integra-tion of various features in one chip, mobile DRAM is required to have not only low power consumption but also high capacity and high speed. To attain these goals in mobile DRAM, we designed a 1Gb single data rate (SDR) Wide-I/O mobile SDRAM with 4 channels and 512 DQ pins, featuring 12.8GB/s data band-width. Figure 28.5.1 shows the chip architecture with 4-channels and 16 segmented 64Mb arrays. The whole chip is made up of 4 partitions which are symmetric with respect to the chip center, and each partition consists of 4×64Mb arrays, peripheral circuits and microbumps. Each channel has its own input pins while external power pins and internal voltage generators are shared with the other channels. In a single channel, 128 data lines are controlled to feed 128 DQs. Four 64Mb arrays in 1-channel can be configured in 4 banks with bank addresses BA [0:1] and row addresses RA [0:11], or in 2 banks with BA [0] and RA [0:12]. In