Towards a scatter-gather architecture
Arun F. Rodrigues, Maya B. Gokhale, Gwendolyn Voskuilen · Proceedings of the International Symposium on Memory Systems · 2019
The on-node performance of High performance computing (HPC) applications is traditionally dominated by memory operations. Put simply, memory is what these applications "do." Unfortunately, they don't do it well. Caches, our first line of attack in the battle for memory performance, often throw away most of the data they fetch before using it. Processor cores, one of our most expensive resources, spend an inordinate amount of time performing simple address computations. Addressing these issues will require new approaches to how on-chip memory is organized and how memory operations are performed. Under Project 38, a joint Department of Energy / Department of Defense architectural resarch project, we have focused on exploring what a flexible in-memory scatter-gather architecture could look like in the context of several important HPC applications.