A FAST AND OPTIMIZED ARCHITECTURE TO PERFORM MULTI-BIT PERMUTATION OPERATION
Sushma Wadar, Dattatraya Shankar Bormane · Helix · 2019
The advanced bit processing operations implemented in the microprocessors and microcontrollers very inefficient.Normally programming techniques are used to emulate the complex bit-related operations.The bit manipulation functions are every now and then required in the areas that are eventually becoming very important.This paper is proposing a techniques which can directly support these bit operations in the form of multimedia shifter unit that can implement standard shifter operations in microprocessors and controllers.The design of the proposed shifter unit is based on the butterfly and inverse butterfly circuits.We show how the proposed design for new shiftes can implement the standard multi-bit scatter and deposit functions found in some processors.The technique proposed in this paper for performing the two operations is based on only Mux.The design of Shifter-Permute functional unit is very challenging work towards its power consumption, speed and area.We have implemented 8-bit Shift-Permute functional unit for bit manipulation and have analyzed the proposed design with the existing design in terms of power consumption, speed and area.Here the circuits are implemented and analyzed by using VHDL and is synthesized by using Xilinx ISE and the targeted device used is Vertex 4 FPGA xc4vlx15-12-sf363 and the same is reflected in the mathematical model purposed for each circuit.