A 32-bank 256 Mb DRAM with cache and TAG
Satoru Tanoi, Y. Tanaka, T. Tanabe, A. Kita, Toshihiro Inada, R. Hamazaki, Y. Ohtsuki, M. Uesugi · 2002
Megabit DRAM design has recently focused both on high data transfer rates and battery operation. To meet the demand for high data-rate memory, this synchronously-operated 32-bank 256 Mb CMOS DRAM has sense amplifier (SA) cache strips and TAGs. The key techniques are: (1) high bit-rate cache operation achieved by 32 8 Mb memory banks supported by the bank-associated shared SA caches and TAG blocks embedded in row decoders, (2) a reduced RAS latency achieved during a bank hit cycle by a bank interleaving scheme, (3) high stability bank control by phase alignment of high-rate timing pulses, and (4) current sensing data-bus amplifier (CSA) scheme with a voltage-controlled negative conductance (VCNC) circuit.>