Networks-on-Chip for heterogeneous 3D Systems-on-Chip
Jan Moritz Joseph · Digitalen Hochschulbibliothek Sachsen-Anhalt (Universitäts- und Landesbibliothek Sachsen-Anhalt) · 2019
Recently proposed manufacturing methods enable the production of heterogeneous 3D System-on-Chips (3D SoCs), in which dies manufactured in different technology nodes are stacked and vertically interconnected. This allows for the combination of components with different electrical requirements on a single chip. One example of such systems are “Vision System-on-Chips” that combine analog image sensors, analog-digital converters and digital signal processing. Communication architectures using the advantages of heterogeneity have not been considered prior to this thesis.We propose Asymmetric 3D Networks-on-chips (A-3D NoCs) for this purpose. A-3D NoCs are NoCs that target heterogeneous 3D SoCs and further exploit the specific properties of silicon dies in disparate technologies. Asymmetry for 3D NoCs is a novel design paradigm, offering advantages in performance, power consumption and area. It further unleashes the full potential of heterogeneous integration for the network itself. The approach of this thesis is twofold: First, we consider A-3D NoCs on a system level to take the advantages of heterogeneous integration for NoC planning including, optimized topology and placement. Second, we improve routers on an architectural and micro-architectural level to tackle technological challenges emerging from heterogeneity. This thesis provides the following specific contributions: The design space of A-3D NoCs is modeled. Technology-specific features are taken into account, in contrast to models for conventional on-chip networks. This results in a deeper understanding of the design space and leads to a systematic approach for its exploration. Next, we propose an analytical approach to system-level optimizations by means of modeling via linear programs for exact solutions and heuristics for efficient solutions. For the first time, models account for technology-specific properties of routers and components. Furthermore, routers and components are placed simultaneously. This combination of models and methods is necessary because properties vary between layers. Area reductions of up to 26.3% over related approaches are possible while maintaining performance of the network. Plus, we achieve white space reductions of up to 21.6% over traditional linear models for placement of components. Thereafter, we propose a comprehensive design and simulation framework including processes for design space exploration and analysis. As a novel feature, it accounts for the described structure and proposed hierarchical order of the design space and it includes technology-specific properties. Furthermore, it considers architectures that are only reasonable due to heterogeneity. This allows for rapid prototyping using parameter sets. Therefore, we propose well-reasoned models. These are implemented in a simulator which is embedded in a design and simulation process, including tools for benchmarking, reporting and analysis. The performance of the simulator is close to state-of-the-art, despite extended features, and it allows for faster design space exploration using parameter sets. Going further, we improve the router architecture by means of better buffer depth and buffer distributions. As a novel feature, memory of routers is divided over heterogeneous layers to reduce area and power in those that are more expensive. This allows for cost reductions. We achieve up to 8.3% area savings and 5.4% power reductions at a minor performance loss of 2.1%; Area reduction of 28% and power savings of 15% are possible at 4.6% performance loss. Hereafter, we optimize routing in A-3D NoCs. For the first time, general principles and models are proposed, which measure the impact of heterogeneity on router area, speed, packet latency and router throughput for any set of commercial technologies. Based on these models, concrete implementations of routing algorithms for heterogeneous 3D SoCs are proposed. Latency reductions of between 1.5x and 6.5x for packets between layers in different technologies and about 1.6x for packets within slow technologies are achieved for a given case study. After that, network throughput reductions are analyzed with the aforementioned models, which are a result of non-purely synchronous communication between routers due to heterogeneity. A co-design of a router architecture with the proposed routing algorithms allows for up to 4x throughput increase with negligible hardware overhead. This thesis comprehensively introduces asymmetry as a novel paradigm for NoCs targeting heterogeneous 3D SoCs. Further, it contributes methods and tools for their design, optimizations on their system level and novel router architectures and microarchitectures. The contributions tackle the most important challenges for implementation of communication networks in heterogeneous 3D systems. Thereby, the design of diverse heterogeneous 3D SoCs is made possible for many new application fields.