DESIGN OF A HIGH SPEED HYBRID TRANSISTOR LOGIC (HTL) MULTIPLIER USING HTL ADDER
P. Manju, T. Madhavi · PONTE International Scientific Researchs Journal · 2019
In cryptographic applications modular multiplications are most widely used. This modular multiplication depends on the addition and shifting operations. While performing iteration operation in modular multiplication, right shift operation with complete word architecture is performed. In the same way arithmetic unit is used in the multiplier to perform the arithmetic operations. While designing arithmetic unit, optimized multipliers are used most widely. Here a high speed hybrid multiplier using hybrid transistor logic adder is presented in this paper. This advanced Montgomery modular multiplication is based on the modular exponentiations to obtain high speed. The Montgomery multiplication uses adequate hardware implementation. The hybrid transistor logic multiplier system not only depends on the modular exponentiations but also depends on the modular multiplication to reduce the delay. Hence compared to Hybrid transistor logic adder system, the hybrid transistor logic multiplier system gives effective results in terms of speed, area and delay.