An Optimized BCH Decoder Design Architecture for Adaptive M-ary Recording Channels
Arvindhan Gunasekaran, Nimisha Chinnu Jose, Shayan Srinivasa Garani · 2019
Error correction codes (ECCs) are used in storage devices to overcome noise and to meet stringent reliability requirements. Multi-level recording channels such as flash, phase change memories etc. require adaptive ECC schemes attuned to the recording channel characteristics that degrade over time. Each bit within M-ary coded data is realized via binary encoding using Bose-Chaudhuri-Hocquenghem (BCH) codes and exchanging side information over M-parallel binary coded channels. Designing optimized BCH decoders becomes critical towards high performance decoding circuits. In this paper, we develop a novel pipelined decoding architecture for BCH codes for such applications. Our proposed architecture is 45.8% more area-efficient than the existing 2-stage pipelined architecture and realized by hardware sharing between the syndrome computation and Chien search stages of the pipeline. Implementation of the proposed design in Kintex-7 field programmable gate array (FPGA) achieves a throughput of 2.11 Gbps and synthesis with UMC's 45 nm technology achieves a throughput of 4.63 Gbps.