Area Optimized Run-time Reconfigurable ALU for Digital Systems
S Jamuna, Puttaraje Gowda Dinesha, Kp Shashikala, K. Kishore Kumar · 2019 Second International Conference on Advanced Computational and Communication Paradigms (ICACCP) · 2019
Present day digital systems are implemented considering the constraints of power, area, speed and cost of the internal logic blocks. Arithmetic logic unit is an essential sub-system block found in almost all digital computing systems. There is a need for reducing the overall design cost. Modern SOC applications are implemented on reconfigurable devices such as the FPGAs with built-in processors. Reconfigurable devices have the advantages of flexibility and high density of logic resources. A careful decision during design process facilitates to obtain a trade-off between system performance and resource utilization. Partial reconfiguration is a feature which extends the capabilities of FPGAs. It allows a portion of the FPGA to be reconfigured while other regions of device continue to work without any interruption. Proposed work aims at implementation of different functionalities over the same resources with a time multiplexing concept. Depending on the requirement a suitable adder or a multiplier is switched in to action without using extra resources. Through this proposed work an effort is made to explore the possibility of run-time reconfiguration as applied to 4 bit ALU design. Hence leading to an efficient utilization of resources available on the device. Comparison of ALU design indicating resource utilization and power consumption with and without partial reconfiguration is given. The design is been executed using XILINX Vivado IDE.