Deriving Low Power Test Sequences Detecting Robust Testable PDFs
Anzhela Yu. Matrosova, Valentina Vladimirovna Andreeva, V. Z. Tychinskiy · 2019
New approach to deriving low power test sequences that detects robust testable PDFs in logical circuits is suggested. Decreasing power consumption is provided by decreasing the number of switches during testing and cutting the sequence length. The approach is based on finding all test pairs consisting of neighbor Boolean vectors for a circuit path. The test pairs are compactly represented by the proper ROBDD. Each pair of neighbor Boolean vectors generates three neighbor Boolean vectors that detect robust testable PDF for both rising and falling transitions. Current approaches are oriented to finding if only one test pair for rising (falling)transition of a circuit path. Applying all test pairs and using intersections of ROBDDs representing these pairs we provide addition facilities to cut power consumption of the test sequences and their lengths. Different algorithms of deriving the test sequences are suggested. Experimental results demonstrate high quality of the test sequences.