Qubit Test Synthesis Processor for SoC Logic
Wajeb Gharibi, David Devadze, Vladimir I. Hahanov, Eugenia I. Litvinova, Ivan Hahanov · 2019
A qubit method for synthesizing tests of discrete functions of SoC components is proposed, which leverages Boolean derivatives with respect to a vector description of logic element's behavior in the form of Q-coverage. The primacy of the metrics of mathematical and technological relations in data structure, on which effective algorithms and methods for controlling or data processing are built to achieve the performance of testing processes, is formulated. A vector model or form of Boolean derivatives is introduced, which is used to synthesize deductive matrices in the qubit fault simulation method and to evaluate the quality of test sequences. A tree-driven ATPG processor, represented by a binary tree-graph of xor-elements for parallel processing of parts of the qubit coverage, and data structures of SoC logic for calculating qubit Boolean derivatives are proposed. The proposed data structures and methods are implemented in a software application that focuses on parallel testing the logic functions of digital systems-on-chips using qubit coverage.