Modulo-(2n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues
Ghassem Jaberipur, Sahar Moradi Cherati · 2019
Diminished-1 (D1) representation of modulo-(2n+ 1) residues in [1, 2n] uses the n-bit codes [0, 2n- 1] and maintains a zero-indicator bit. Such D1 encoding has led to efficient parallel prefix modulo-(2n+ 1) adders that perform as fast as the companion modulo-(2n- 1) and -2nadders with (3 + 2 log n)△ delay, where △ denotes the delay of a simple 2-input gate. Also similar, but slower (i.e., with one △ more delay) and slightly more complex, parallel prefix architectures have been offered for modulo-(2n- 3) adders. On the other hand, reverse conversion schemes for 4and 5-moduli sets that include conjugate moduli pairs 2n± 1 and 2n± 3 are already available, while we have not encountered any efficient modulo(2n+ 3) adder. Therefore, in this paper, we offer the diminished-3 (D3) representation of modulo-(2n+ 3) residues that maps the residue interval [3, 2n+ 2] to [0, 2n- 1] and maintains a 2-bit {0,1, 2}-indicator. The corresponding parallel prefix adder, which performs as fast as the fastest previous modulo-(2n- 3) adder is designed, where a 3-way compound architecture is devised as the bulk of modular addition that yields sum, sum+1, and sum+2. The proposed architecture is fully synthesized via Synopsis Design Compiler and tested for correctness, and its figures of merit compared with modulo(2n- 3) and -(2n+ 1) adders.