Performance Analysis of Convolutional encoder based on FPGA
Sudeep Giri, Pritesh Patil, P.B. Murmude · 2019
This paper focuses on performance analysis of convolution encoder based on FPGA. With the big quantity of applications now a days, that use digital communication to store and retrieve data, this information should sent and received with smallest errors. Forward Error Correction (FEC) schemes unit a necessary an area of wireless communication systems. There square measure several styles of cryptography techniques accustomed correct utterly totally different error. Convolution secret writing methodology, an honest technique used for correcting errors that occur throughout data transmission. A The performance analysis is implemented by using Vivado 2016.1 and Xilinx Simulation. FPGA device used for hardware realization of Convolutional encoder performed with the help of XC7Z020clg4843. Convolutional encoders area unitenforced within the sort of a register style of circuit with explicit locations of the register completely ORed along to supply AN output. The locations that area unit completely ORed along is also mentioned as faucets. The location of those faucets defines potential state transitions wherever the amount of states for a selected code is outlined by 2(L+1). During this case, L is that the length of the register. Using this results in paper it is found that error correcting codes are the best medium to triumph data corruption in digital communication channels.