RTL bug localization through LTL specification mining (WIP)
Vighnesh Iyer, Donggyu Kim, Borivoje Nikolić, Sanjit A. Seshia · 2019
As the complexity of contemporary hardware designs continues to grow, functional verification demands more effort and resources in the design cycle than ever. As a result, manually debugging RTL designs is extremely challenging even with full signal traces after detecting errors in chip-level software simulation or FPGA emulation. Therefore, it is necessary to reduce the burden of verification by automating RTL debugging processes.