Vertical-channel stacked array (VCSTAR) for 3D NAND flash memory
Yoon Kim, Se Hwan Park, Wandong Kim, Joo Yon Seo, Byung‐Gook Park · 2011
Recently, 3D stacked NAND flash architectures have been proposed to solve scaling limit of the planar NAND flash memory based on floating-gate type [1]-[2]. However, theses structures have several drawbacks. For TCAT[1], declined hole-etch slope leads to different curvature radius of each stacked active layers. Consequently, different electric field is applied to each layer in program operation, which causes the threshold voltage distribution problem. In case of VSAT[2], it is almost impossible to implement metal gate structure. Also, VSAT has the limitation of the stacking extendability due to inefficient bit line current flow (going up and down).