Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone
Yvain Thonnart, Pascal Vivet, Shikhanshu Agarwal, Ramesh Chauhan · 2019
Thanks to their intrinsic pipelining and their globally-asynchronous locally-synchronous nature, quasi-delay-insensitive asynchronous networks on chip can provide high throughput and low latency especially suited to chip-level interconnect. We present the substitution of the multi-clock-domain NoC of a Qualcomm mobile platform by an equivalent ANoC robust asynchronous NoC, relying on the existing network interfaces and automated tools, with a hierarchical substitution of the NoC backbone. Given a raw data-rate twice-higher than the synchronous NoC allowing in-network serialization by two, we show that this integration of an asynchronous NoC can improve system latency or area by 24% with no degradation of throughput and minimal impact on peak power consumption.