Nested Hardware Architecture for Self-Organizing Map
Hiroomi Hikawa · 2019
This paper proposes a hardware SOM architecture with nested structure. The proposed hardware SOM is made of a single module, and the module is made of four smaller modules, then the smaller module consists of four further smaller modules. With this simple recursive structure, size of SOM can be easily increased. In addition, the proposed SOM requires only one clock cycle to process a single input vector, and hence very high throughput operation is provided. Experimental results show that that the proposed SOM architecture provides he scalability without degrading the performance, and the proposed SOM achieved 33024 MCUPS of high throughput.