Performance Analysis of Idea Algorithm on FPGA for Data Security
G S Pushpalatha · International Journal for Research in Applied Science and Engineering Technology · 2019
Data security is important issue in computer networks. Cryptographic algorithms are essential parts in network security. There are plenty of algorithms for the purpose of security. IDEA is one among the proposed algorithm. International Data Encryption Algorithm is symmetric encryption algorithm which is widely used for the purpose of security with simple arithmetic operation. This paper presents an FPGA implementation of IDEA encryption and decryption using Verilog HDL on Spartan 3. It is further implemented for image encryption and decryption using MATLAB. The usage of 128-bit key control makes this algorithm secure and reliable. Experimental synthesis result shows that the proposed design is better where, the delay is reduced to 212.498ns and only 1% of available memory resource is used.