Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies
Shubham Rai, Ansh Rupani, Pallab Nath, Akash S. Kumar · 2019
We present here two watermarking techniques as a countermeasure to IC overbuilding and IP piracy by employing an encoding scheme using polymorphic inverter designs based on reconfigurable nanowire technologies. We employ a fabrication method unique to nanowire technologies which enables fixing of a node in the logic network to either 0 or 1. This technique allows fixing implicit don't care nodes to drive polymorphic inverters in a predetermined way, thereby contributing to the watermark. For a 64-bit signature, an area overhead of 0.72% and 2.14%, and an extremely low average probability of coincidence of 3.3×10-47and 3.52×10-53are obtained for our watermarking techniques for EPFL and IWLS benchmarks.