Crypto-Based Dual-Phase Hardware Steganography for Securing IP cores
Anirban Sengupta, Mahendra Rathor · Letters of the IEEE Computer Society · 2019
In an untrustworthy foundry, an intellectual property (IP) core is susceptible to piracy. Moreover, an adversary can deceitfully claim the ownership of a pirated IP core. In such cases of ownership conflict, the true ownership of an IP core should be provable. This letter presents a novel approach of securing IP cores against piracy/ false claim of ownership using crypto-based dual phase hardware steganography. By detecting the embedded robust stego-mark in the design, the ownership can be awarded to the genuine IP owner. The paper presents a novel security algorithm that leverages crypto-modules and security properties to generate stego-constraints and embeds them into a hardware IP design during two distinct phases of behavioural synthesis. Because of using large size stego-keys and embedding steganography at two distinct phases, the proposed approach achieves robust security and high reliability than existing recent approaches.