An expandable topology with low wiring congestion for silicon interposer‐based network‐on‐chip systems
Sajed Dadashi, Midia Reshadi, Akram Reza, Ahmad Khademzadeh · Transactions on Emerging Telecommunications Technologies · 2019
Abstract In 2.5D stacking technology, multiple chips have stacked side‐by‐side on a silicon interposer layer. The network‐on‐chip in the central processing unit (CPU) layer makes it possible to connect processing cores to each other. The interposer layer prepares the connection between the CPU cores and other chips such as memory chip. The memory chip usually contains several segments stacked vertically. The network‐on‐chip can be extended to the interposer layer to make use of unused routing resources of the interposer. Applying an efficient topology and deadlock‐free routing algorithm on the CPU layer and interposer layer is essential. In this paper, a new topology and routing algorithm are proposed to use on the CPU layer as well as on the interposer layer for creating a uniform interconnection network to decrease delay and power consumption. This topology is scalable and can be used simply for extensive networks. Most of interposer layer topologies are not scalable and have a lot of crossed links. Moreover, it is required to increase the degree of routers connected to memory segments. The proposed topology uses a few crossed links compared to other proposed interposer layer topologies. There will be some similar small sub‐networks that fairly connected together with intermediate routers. Furthermore, this topology can be extended in a hierarchical manner.