INVITED: The Metric Matters: The Art of Measuring Trust in EIectronics
Jonathan Cruz, Prabhat Mishra, Swarup Bhunia · Design Automation Conference · 2019
Electronic hardware trust is an emerging concern for all stake-holders in the semiconductor industry. Trust issues in electronic hardware span all stages of its life cycle-from creation of intellectual property (IP) blocks to manufacturing, test and deployment of hardware components and all abstraction levels-from chips to printed circuit boards (PCBs) to systems. The trust issues originate from a horizontal business model that promotes reliance of third-party untrusted facilities, tools, and IPs in the hardware life cycle. Today, designers are tasked with verifying the integrity of third-party IPs before incorporating them into system-on-chip (SoC) designs. Existing trust metric frameworks have limited applicability since they are not comprehensive. They capture only a subset of vulnerabilities such as potential vulnerabilities introduced through design mistakes and CAD tools, or quantify features in a design that target a particular Trojan model. Therefore, current practice uses ad-hoc security analysis of IP cores. In this paper, we propose a vector-based comprehensive coverage metric that quantifies the overall trust of an IP considering both vulnerabilities and direct malicious modifications. We use a variable weighted sum of a design’s functional coverage, structural coverage, and asset coverage to assess an IP’s integrity. Designers can also effectively use our trust metric to compare the relative trustworthiness of functionally equivalent third-party IPs. To demonstrate the applicability and usefulness of the proposed metric, we utilize our trust metric on Trojan-free and Trojan-inserted variants of an IP. Our results demonstrate that we are able to successfully distinguish between trusted and untrusted IPs.