VLSI Architecture for Systolic-Like Modular Multipliers over GF (2m) Build on Irreducible All-One Polynomials
M Soumya. · International Journal for Research in Applied Science and Engineering Technology · 2019
By using irreducible AOP, an effective recursive formulation is proposed implies systolic implementation of these finite field multiplications over GF (2 m ). Here, a recursive algorithm derived for the multiplication and used it in designing a systematic and localized bit-linear dependence graph for computing systolic multiplication. This dependence graph is altered to a fine-grained dependence graph (DG) by using node splitting method. This parallel systolic architecture is mapped from finegrained DG. Compared to other structures, it doesn't include any global communication for reducing the modules. The proposed architecture has same time compared to other existent bit-parallel systolic structure and includes registers to a lesser extent. This proposed structure has an ascendable latency of l+ [log 2 s] +1 cycles which is minimum compared with existing designs. This structure is proposed specifically for hardware complexity in the structure and throughput scalability to meet the area-time tradeoff by maintaining the overall latency in resource-constrained application.