Block Level SoC Verification Using Systemverilog
Krishnan K Yadu, Ramesh Bhakthavatchalu · 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA) · 2019
Introducing a new strategy for verification of System On Chip (SoC) using system Verilog. System Verilog provides a great platform for verification. The OOPs concept in System Verilog make it more reliable. There are many existing SoC verification methods are available. But most of them are not that much efficient. So here we are planning to introduce a new verification strategy that takes many of the positive characteristics of the existing strategies and mixes them together to have an efficient and perfect strategy by using the advantages of System Verilog.