Novel Reliable QCA Subtractor Designs using Clock zone based Crossover
Marshal Raj, Lakshminarayanan Gopalakrishnan · 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA) · 2019
The rising challenges faced by CMOS technology has urged the researchers to find alternatives to it at extreme nm levels. Among the several proposed alternatives, Quantum-dot Cellular Automata is one of the prominent alternatives that offers High speed, Small area, Low power and High packaging density. Subtractor are used for different applications in many signal processing systems. In this paper, three full subtractor designs are proposed in QCA using Majority logic. The existing designs are implemented using rotated cell crossover and multilayer crossover are vulnerable to faults. The proposed designs are implemented using Clock zone based crossover approach and hence, they are more resistant to fabrication defects. The proposed designs can be extended to implement n-bit subtractor design. The proposed designs are validated in QCADesigner 2.0.3 using Coherence vector simulation engine.