Verification and Fault Localization for VHDL Programs
Roderick Bloem, Franz Wotawa · 2002
During the last decades, hardware-design languages like Verilog and VHDL have become very common for designing digital circuits. These languages allow designers to specify and test the behavior of circuits before they are produced. This helps to avoid incorrect designs and saves money, providing that the designs are rigorously tested. If faulty behavior is