Combining Clock and Voltage Noise Countermeasures Against Power Side-Channel Analysis
Jacqueline Lagasse, Christopher Bartoli, Wayne P. Burleson · 2019
The power side-channel continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the more popular countermeasures incurring 3-4x overhead in area and power. While this is acceptable for some devices, other lightweight devices can not tolerate this amount of overhead. In addition, most countermeasures are quite invasive to the design process, requiring modification to the design and additional validation. This work explores two relatively non-invasive countermeasures, both the detailed implementations and the interactions: 1) clock randomization, and 2) supply voltage noise, by real collecting power traces from a state-of-the-art FPGA board and using the Correlation Power Analysis (CPA) attack. Counter-attacks and their impact on the countermeasure efficacy are also explored. The key result is that the combined effects of the two countermeasures is greater than the impact of either countermeasure when used independently.