Enhanced Architecture for Precision Adders
N.G. Archana, Prameela Kumari · 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA) · 2019
One of the basic and most important part of any circuit is an adder. It is used to compute highly complicated signals in many DSP applications. These signals are represented using standard IEEE floating point representation in real-time which are very tedious to process. One of the most widely accepted adder in all wired and wireless application is the IEEE based standard 754 adder. It adds two single precision floating point values. As the precision increases, there is also an increase in the complexity in calculations. Hence, there is a need to enhance the architecture of this floating point adder. In this paper we propose 4 stages of pipelined architecture to enhance the speed of computation thus reducing the overall delay.