"Vector Arithmetic Unit Design Using FXP-HNS Technique for Power, Delay and Area optimization"
Gopisingh Naik, Pratibha Shingare · 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA) · 2019
In 3D handheld graphics processors, Vector arithmetic unit is an unavoidable part for vector operations. The handheld devices are small screen devices. The resolution of it is less but its power and area must be optimized while designing. For these devices, vector operations can be done with fixed point hybrid logarithmic number system technique (FXP-HNS). This technique gives faster operations with optimized power, delay and area. We are proposing hardware which is compatible for vector operations like Additions / Subtractions, Multiplication/ Division, Square-root. for 32-bit Fixed point Hybrid Logarithmic number system format input in Xilinx 14.7 tool.The proposed designed hardware verified on 180nm, 90nm and 45nm technologies using CADENCE Encounter tool. The respective total power requirements are 820.5μw, 239.8μw and 116.7μw for 180nm, 90nm and 45nm technologies. The time requirements for operations are 20590ps, 15036ps and11383ps respectively.The proposed hardware gives optimized & efficient results with 45nm technology for vector arithmetic operations. Which is also efficient for Fixed point (FXP) and Floating point (FLP) operations with programmable arithmetic pointer in FXP-HNS technique.