Development of a Random Test Generator for Multi-Core Processor Design Verification
Mohd Leesan Ul Aktab, H. V. Ravish Aradhya, Furqan Saberi · 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA) · 2019
Design verification is the task of verifying the design logic and the functional correctness of the design. The ever-growing complexity of the processor design is also growing the complexity of verification too. So, there is a need of automated tool that has the capability to hit the corner cases of the design and helps to ease the work of design verification. In this study we introduce an inhouse developed stress test tool which helps to provide stimulus for complex multiprocessor design for memory subsystem which is customized for ARMv8 core processor design. This tool demonstrates highly effective leveraging of ARMv8 PMUv3 to calibrate/grade stress tests in real time and by making use of its features to quickly come up with complex directed test cases for stress testing or bug hunting. It makes use multiple algorithms, PMU events and the test cases to verify the design. It has been observed that the tool developed has the capability to hit the performance bottleneck to verify the design by running random tests on design under test.