Study and Analysis of Various LFSR Architectures
Roshni Oommen, Merin K George, Sharon Joseph · 2018
In large scale integration process, lots of transistors are implanted on a single silicon substrate for setting up of intricate circuits. Accordingly, major problem of power dissipation comes into the picture. Linear Feedback Shift Register (LFSR) is a commonly used pseudo random sequence generator to generate random 1s and 0s. It is used in applications such as Built-in-self test (BIST), cryptography etc. LFSR's are having high level of fault coverage so they are used in several coding schemes. In this paper, LFSR is implemented using Complementary Metal Oxide Semiconductor (CMOS), Gate Diffusion Input (GDI), modified GDI(mGDI) and Multi Threshold CMOS (MTCMOS) techniques in Cadence Virtuoso using 180nm technology. Simulations of these circuits are done and different parameters like power, propagation delay and area are compared. mGDI gives a reduction of 30%, 39%, 49% with respect to CMOS in power, delay and area respectively and a reduction of 6%, 14% with respect to GDI in power, and delay respectively. Thus, mGDI LFSR design can be employed for low power testing.