3D Integration of CMOS-Compatible Surface Electrode Ion Trap and Silicon Photonics for Scalable Quantum Computing
Jing Tao, Yu Dian Lim, Hong Yu Li, Nam Piau Chew, Anak Agung Alit Apriyana, Lin Bu, Peng Zhao, Luca Guidoni, Chuan Seng Tan · 2019
In this work, we report ion trap fabrication using prevailing foundry copper back-end-of-line process on a 300mm Si platform. Surface electrodes comprising of ~3.7 µm thick Cu and ~0.2 µm thick of Au surface finish are electroplated above a ~3 µm thick of SiO2 layer on a high-resistivity Si substrate. The innovative process, which is fully compatible with CMOS back-end, enables a fine gap trench structure between the electrodes, such that the exposed dielectric area to the trapped ions is reduced. By optimizing the electroplating process, a relatively flat Cu surface is created with a thin Au layer deposited as an effective protective layer to prevent surface oxidation. The fabricated trap is wire-bonded in a CPGA package for DC and RF testing. Small size Si traps show a good RF dissipation property which is a prerequisite for ion trapping. The further integration of TSV and Si photonics shows a promising prospect in terms of electrical and optical performance enhancement of ion trap.