Low Cost Flip-Chip Stack for Partitioning Processing and Memory
Fabian Hopsch, Andy Heinig · 2019
This paper presents a novel chip-to-chip packaging approach. Most nowadays systems comprise a least a processing unit and some memory for storing data. Rising bandwidth requirements, bring up new types of memory. This is achieved by increasing the clocking and/or using wider interfaces. But raised frequency leads to more effort on the communication channel in terms of signal integrity. The packaging approach presented here, results in a very short communication channel between memory and processor and with achieving high-performance while keeping the communication effort low. The requirements for the IO-cells are reduced, because of this short channel, leading to very small interfaces. All together the solution is a low-cost flip-chip stacking in terms of design and packaging costs.