FPGA Implementation of Reed Solomon Encoder and Decoder
Saurabh Singh, Mohan Khambalkar, A. V. S. S. Varma · Current Trends in Signal Processing · 2019
Abstract: Forward Error Correcting (FEC) is a technique employed to enhance data security & reliability. An efficient coding technique is essential to ensure data security. Reed Solomon Codes are widely used to provide error correction capability against burst error. This paper presents the design & FPGA implementation of RS (7, 3) codes. The design is entirely parameterized and can be scaled readily for a wide range of a number of message symbols. Keywords: FEC, Galois field, Reed Solomon codes, RS encoder, RS decoder Cite this Article Saurabh Singh, Mohan Khambalkar, Ankur Varma. FPGA Implementation of Reed Solomon Encoder and Decoder. Current Trends in Signal Processing. 2019; 9(1): 10–16p.