Effect of Frequency on Energy Efficient Transceiver Design
Keshav Kumar, Dil Muhammad Akbar Hussain, Bishwajeet Pandey · Gyancity Journal of Engineering and Technology · 2019
We have observed the different chip power which are clustered on UART device, example IOs, leakage and total power. This through experiment is done at a frequency of 1 GHz, having a duty cycle of 50% and 1ns time period. We did our experiment with Virtex 4, Virtex 5, Virtex 6, Spartan3 and Spartan 6 FPGA. In the experiment we found Spartan 6 uses the least amount of power among all the FPGA used in the experiment.