The Intelligent Cache Controller of a Massively Parallel Processor JUMP-1
Masahiro Goshima · 1997
This paper describes the intelligent cache controller of JUMP-1, a distributed shared memory type MPP. JUMP-1 adopts an off-the-shelf superscalar as the element processor to meet the requirement of peak performance, but such a processor lacks the ability to hide inter-processor communication latency, which may easily become too long on MPPs. Therefore JUMP-1 provides an intelligent memory system to remedy the week point. The cache controller is one of the main components of the memory system, and provides many cache-level supports for inter-processor communication; explicit cache control, high-bandwidth cache prefetching, and a few types of synchronization structures for fine-grained message communication.