Power Efficient Design of Semi-Dynamic Master-Slave Single-EdgeTriggered Flip-Flop
Imran Ahmed Khan, Mirza Tariq Beg · International Journal on Electrical Engineering and Informatics · 2019
In this work, eight existing master slave single-edge-triggered flip-flops have been analyzed in 130nm process node.A new master slave single-edge-triggered flip-flop has also been proposed.The proposed flip-flop is compared with the existing flip-flops on the basis of power consumption, propagation delay and power delay product (PDP).Special emphasis has been given to power consumption.The power performance of all flip-flops as a function of supply voltage, clock frequency and data activity has been observed.TSpice results of power consumption show that the proposed flip-flop design excels rival designs for all supply voltages; all clock frequencies and all data patterns.Thus the proposed flip-flop is most power efficient flip-flop.This flip-flop also shows the third shortest delay and the second lowest PDP among all discussed flip-flops.The proposed flip-flop is best suitable for systems where low power and low area is of primary interest within a certain timing budget.